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authorCayetano Santos <csantosb@inventati.org>2025-05-26 16:41:44 +0200
committerSharlatan Hellseher <sharlatanus@gmail.com>2025-06-12 08:55:18 +0100
commit8730c8f3a86ef41d5b88df573fce9b6d73c23b0c (patch)
treec48711ee16c122310f562d076daa49f6d5ddfa8b
parent356cc64411f7fa2c2dbf35f72f8be4957f00dce0 (diff)
gnu: Add python-cocotb.
* gnu/packages/electronics.scm (python-cocotb): New variable. Change-Id: I8816e137002ad6763a466c8c79353489d3d3cc2e Reviewed-by: Maxim Cournoyer <maxim.cournoyer@gmail.com> Signed-off-by: Sharlatan Hellseher <sharlatanus@gmail.com>
-rw-r--r--gnu/packages/electronics.scm46
1 files changed, 46 insertions, 0 deletions
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm
index 5910b5cc39..821ba19f55 100644
--- a/gnu/packages/electronics.scm
+++ b/gnu/packages/electronics.scm
@@ -561,6 +561,52 @@ formats.")
for sigrok.")
(license license:gpl3+)))
+(define-public python-cocotb
+ (package
+ (name "python-cocotb")
+ (version "1.9.2")
+ (source
+ (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/cocotb/cocotb")
+ (commit (string-append "v" version))))
+ (file-name (git-file-name name version))
+ (sha256
+ (base32 "19mybnhqa2jz134jj8686310fniav5nldiq0y7kbgml81ppai87c"))))
+ (build-system pyproject-build-system)
+ (arguments
+ (list
+ #:test-flags
+ ;; Tests requiring a verilog simulator.
+ #~(list "-k" (string-join
+ (list "not parallel_cocotb"
+ "cocotb"
+ "vhdl_libraries_multiple")
+ " and not "))
+ #:phases
+ #~(modify-phases %standard-phases
+ ;; Tests requiring a vhdl simulator.
+ (add-after 'check 'check-vhdl
+ (lambda* (#:key tests? #:allow-other-keys)
+ (when tests?
+ (setenv "SIM" "nvc")
+ (invoke "pytest" "-vv" "-k" "vhdl_libraries_multiple")))))))
+ (native-inputs
+ (list iverilog
+ nvc
+ python-pytest
+ python-setuptools
+ python-wheel))
+ (propagated-inputs
+ (list python-find-libpython))
+ (home-page "https://github.com/cocotb/cocotb")
+ (synopsis "Library for writing HDL test benches in Python")
+ (description
+ "Coroutine based cosimulation test bench environment for verifying VHDL
+and Verilog RTL using Python.")
+ (license license:bsd-3)))
+
(define-public python-edalize
(package
(name "python-edalize")