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| author | Efraim Flashner <efraim@flashner.co.il> | 2023-07-04 11:53:09 +0300 |
|---|---|---|
| committer | Efraim Flashner <efraim@flashner.co.il> | 2025-03-13 14:34:58 +0200 |
| commit | 68fe63ab7b9cc0d57f7a9d70a8a4e96bab7cd40d (patch) | |
| tree | f205040b18376523b88ea31e89e1159921a81ea1 | |
| parent | 5f54bb4c8e007ea463e41f597db23ac80e77e6ad (diff) | |
fixup node-12 riscv64 support
| -rw-r--r-- | gnu/packages/patches/node-12-riscv64-support.patch | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/gnu/packages/patches/node-12-riscv64-support.patch b/gnu/packages/patches/node-12-riscv64-support.patch index bf10b4608a..1450c228ae 100644 --- a/gnu/packages/patches/node-12-riscv64-support.patch +++ b/gnu/packages/patches/node-12-riscv64-support.patch @@ -33062,10 +33062,10 @@ index 766ce71db11..7a1376ce1c0 100644 #endif diff --git a/deps/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h b/deps/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h new file mode 100644 -index 00000000000..837ff0d5718 +index 00000000000..77691b1c433 --- /dev/null +++ b/deps/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h -@@ -0,0 +1,2642 @@ +@@ -0,0 +1,2650 @@ +// Copyright 2021 the V8 project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. @@ -34393,6 +34393,7 @@ index 00000000000..837ff0d5718 + //TurboAssembler::CompareI(dst, lhs.gp(), Operand(rhs.gp()), cond); +} + ++/* +namespace liftoff { + +inline FPUCondition ConditionToConditionCmpFPU(Condition condition, @@ -34424,21 +34425,28 @@ index 00000000000..837ff0d5718 +} + +} // namespace liftoff ++*/ + +void LiftoffAssembler::emit_f32_set_cond(Condition liftoff_cond, + Register dst, DoubleRegister lhs, + DoubleRegister rhs) { ++ /* + bool predicate; + FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(liftoff_cond, &predicate); + TurboAssembler::CompareF32(dst, fcond, lhs, rhs); ++ */ ++ bailout(kUnsupportedArchitecture, "emit_f32_set_cond"); +} + +void LiftoffAssembler::emit_f64_set_cond(Condition liftoff_cond, + Register dst, DoubleRegister lhs, + DoubleRegister rhs) { ++ /* + bool predicate; + FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(liftoff_cond, &predicate); + TurboAssembler::CompareF64(dst, fcond, lhs, rhs); ++ */ ++ bailout(kUnsupportedArchitecture, "emit_f64_set_cond"); +} + +/* |