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| author | Marius Bakke <marius@gnu.org> | 2020-07-24 23:53:17 +0200 |
|---|---|---|
| committer | Marius Bakke <marius@gnu.org> | 2020-07-24 23:53:17 +0200 |
| commit | cbe96f14700f4805552c47d5f163a75c35f86575 (patch) | |
| tree | d7791d29b283507bb8953a292d764b24774c955c /gnu/packages/fpga.scm | |
| parent | 337333c2567bdf767fdc8e04520c4bc0c8b33784 (diff) | |
| parent | 7a9a27a051a04a7fee2e7fe40127fedbe9112cfd (diff) | |
Merge branch 'master' into staging
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index fda5de60c7..b2717d2233 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -127,7 +127,7 @@ For synthesis, the compiler generates netlists in the desired format.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cliffordwolf/yosys.git") + (url "https://github.com/cliffordwolf/yosys") (commit (string-append "yosys-" version)) (recursive? #t))) ; for the ‘iverilog’ submodule (sha256 @@ -223,7 +223,7 @@ For synthesis, the compiler generates netlists in the desired format.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cliffordwolf/icestorm.git") + (url "https://github.com/cliffordwolf/icestorm") (commit commit))) (file-name (git-file-name name version)) (sha256 @@ -304,7 +304,7 @@ FOSS FPGA place and route tool.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/YosysHQ/arachne-pnr.git") + (url "https://github.com/YosysHQ/arachne-pnr") (commit commit))) (file-name (git-file-name name version)) (sha256 |