diff options
| -rw-r--r-- | gnu/packages/fpga.scm | 14 | 
1 files changed, 13 insertions, 1 deletions
| diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index bb199096dc..a344e8ed2e 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -1,5 +1,6 @@  ;;; GNU Guix --- Functional package management for GNU  ;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org> +;;; Copyright © 2016 Theodoros Foradis <theodoros.for@openmailbox.org>  ;;;  ;;; This file is part of GNU Guix.  ;;; @@ -31,7 +32,9 @@    #:use-module (gnu packages bison)    #:use-module (gnu packages flex)    #:use-module (gnu packages gtk) +  #:use-module (gnu packages graphviz)    #:use-module (gnu packages libffi) +  #:use-module (gnu packages linux)    #:use-module (gnu packages zip)    #:use-module (gnu packages perl)    #:use-module (gnu packages ghostscript) @@ -136,6 +139,13 @@ For synthesis, the compiler generates netlists in the desired format.")                            (string-append "PREFIX=" %output))         #:phases         (modify-phases %standard-phases +         (add-before 'configure 'fix-paths +           (lambda _ +             (substitute* "./passes/cmds/show.cc" +               (("exec xdot") (string-append "exec " (which "xdot"))) +               (("dot -") (string-append (which "dot") " -")) +               (("fuser") (which "fuser"))) +             #t))           (replace 'configure             (lambda* (#:key inputs (make-flags '()) #:allow-other-keys)               (zero? (apply system* "make" "config-gcc" make-flags)))) @@ -172,7 +182,6 @@ For synthesis, the compiler generates netlists in the desired format.")                          (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""                                                                  iverilog "\"")))                       #t)))))) -    ;; TODO add xdot [patch the path to it here] as soon as I find out where it is.      (native-inputs       `(("pkg-config" ,pkg-config)         ("python" ,python) @@ -185,6 +194,9 @@ For synthesis, the compiler generates netlists in the desired format.")       `(("tcl" ,tcl)         ("readline" ,readline)         ("libffi" ,libffi) +       ("graphviz" ,graphviz) +       ("psmisc" ,psmisc) +       ("xdot" ,xdot)         ("abc" ,abc)))      (home-page "http://www.clifford.at/yosys/")      (synopsis "FPGA Verilog RTL synthesizer") | 
