From 3119142ea31ec13a64fbb6246f40ca9315b49b21 Mon Sep 17 00:00:00 2001 From: Vagrant Cascadian Date: Sun, 15 Jun 2025 02:19:50 +0000 Subject: [PATCH 1/3] Revert "drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0" This reverts commit d2b58a10228a906d46155eb7c15d79f39be25b37. --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 34 -------------------- 1 file changed, 34 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 5d7df4c3b08c..2aab2a095678 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -157,7 +157,6 @@ struct vop2_video_port { struct drm_crtc crtc; struct vop2 *vop2; struct clk *dclk; - struct clk *dclk_src; unsigned int id; const struct vop2_video_port_data *data; @@ -212,7 +211,6 @@ struct vop2 { struct clk *hclk; struct clk *aclk; struct clk *pclk; - struct clk *pll_hdmiphy0; /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -221,8 +219,6 @@ struct vop2 { struct vop2_win win[]; }; -#define VOP2_MAX_DCLK_RATE 600000000 - #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \ (x) == ROCKCHIP_VOP2_EP_HDMI1) @@ -1055,9 +1051,6 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); - if (vp->dclk_src) - clk_set_parent(vp->dclk, vp->dclk_src); - clk_disable_unprepare(vp->dclk); vop2->enable_count--; @@ -2078,27 +2071,6 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); - /* - * Switch to HDMI PHY PLL as DCLK source for display modes up - * to 4K@60Hz, if available, otherwise keep using the system CRU. - */ - if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { - drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { - struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - - if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { - if (!vp->dclk_src) - vp->dclk_src = clk_get_parent(vp->dclk); - - ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI0 PHY PLL: %d\n", ret); - break; - } - } - } - clk_set_rate(vp->dclk, clock); vop2_post_config(crtc); @@ -3270,12 +3242,6 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->pclk); } - vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0"); - if (IS_ERR(vop2->pll_hdmiphy0)) { - drm_err(vop2->drm, "failed to get pll_hdmiphy0\n"); - return PTR_ERR(vop2->pll_hdmiphy0); - } - vop2->irq = platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); -- 2.50.0