diff options
Diffstat (limited to 'gnu/packages/electronics.scm')
| -rw-r--r-- | gnu/packages/electronics.scm | 1821 |
1 files changed, 1650 insertions, 171 deletions
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm index a13ad2196a..58c932e5c3 100644 --- a/gnu/packages/electronics.scm +++ b/gnu/packages/electronics.scm @@ -1,16 +1,26 @@ ;;; GNU Guix --- Functional package management for GNU -;;; Copyright © 2017 Theodoros Foradis <theodoros@foradis.org> +;;; Copyright © 2016, 2017, 2018 Theodoros Foradis <theodoros@foradis.org> ;;; Copyright © 2018–2021 Tobias Geerinckx-Rice <me@tobias.gr> ;;; Copyright © 2019 Clément Lassieur <clement@lassieur.org> -;;; Copyright © 2021 Efraim Flashner <efraim@flashner.co.il> +;;; Copyright © 2021, 2024 Efraim Flashner <efraim@flashner.co.il> ;;; Copyright © 2021 Leo Famulari <leo@famulari.name> -;;; Copyright © 2022, 2023 Maxim Cournoyer <maxim.cournoyer@gmail.com> +;;; Copyright © 2022, 2023, 2025 Maxim Cournoyer <maxim@guixotic.coop> ;;; Copyright © 2024 Juliana Sims <juli@incana.org> ;;; Copyright © 2025 Cayetano Santos <csantosb@inventati.org> ;;; Copyright © 2025 Sharlatan Hellseher <sharlatanus@gmail.com> ;;; Copyright © 2022 Konstantinos Agiannis <agiannis.kon@gmail.com> -;;; Copyright © 2018-2021 Tobias Geerinckx-Rice <me@tobias.gr> ;;; Copyright © 2015-2025 Ricardo Wurmus <rekado@elephly.net> +;;; Copyright © 2022, 2024, 2025 Artyom V. Poptsov <poptsov.artyom@gmail.com> +;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org> +;;; Copyright © 2019 Amin Bandali <bandali@gnu.org> +;;; Copyright © 2020 Vinicius Monego <monego@posteo.net> +;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw> +;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au> +;;; Copyright © 2022 jgart <jgart@dismail.de> +;;; Copyright © 2023 Simon South <simon@simonsouth.net> +;;; Copyright © 2024 Jakob Kirsch <jakob.kirsch@web.de> +;;; Copyright © 2025 Zheng Junjie <873216071@qq.com> +;;; Copyright © 2022, 2025 Evgeny Pisemsky <mail@pisemsky.site> ;;; ;;; This file is part of GNU Guix. ;;; @@ -30,9 +40,14 @@ (define-module (gnu packages electronics) #:use-module ((guix licenses) #:prefix license:) #:use-module (guix build-system cmake) + #:use-module (guix build-system copy) #:use-module (guix build-system glib-or-gtk) #:use-module (guix build-system gnu) + #:use-module (guix build-system meson) #:use-module (guix build-system pyproject) + #:use-module (guix build-system python) + #:use-module (guix build-system qt) + #:use-module (guix deprecation) #:use-module (guix download) #:use-module (guix gexp) #:use-module (guix git-download) @@ -42,49 +57,257 @@ #:use-module (gnu packages algebra) #:use-module (gnu packages autotools) #:use-module (gnu packages base) + #:use-module (gnu packages bash) #:use-module (gnu packages bison) #:use-module (gnu packages boost) #:use-module (gnu packages c) #:use-module (gnu packages check) #:use-module (gnu packages cmake) #:use-module (gnu packages compression) + #:use-module (gnu packages cpp) #:use-module (gnu packages documentation) + #:use-module (gnu packages elf) #:use-module (gnu packages engineering) #:use-module (gnu packages embedded) #:use-module (gnu packages flex) + #:use-module (gnu packages freedesktop) #:use-module (gnu packages fontutils) - #:use-module (gnu packages fpga) #:use-module (gnu packages gawk) #:use-module (gnu packages gd) + #:use-module (gnu packages gdb) + #:use-module (gnu packages gettext) + #:use-module (gnu packages ghostscript) #:use-module (gnu packages gl) #:use-module (gnu packages glib) #:use-module (gnu packages gnome) + #:use-module (gnu packages gperf) #:use-module (gnu packages graphviz) #:use-module (gnu packages gtk) + #:use-module (gnu packages libffi) #:use-module (gnu packages libftdi) #:use-module (gnu packages libusb) #:use-module (gnu packages linux) + #:use-module (gnu packages llvm) + #:use-module (gnu packages man) #:use-module (gnu packages maths) #:use-module (gnu packages m4) #:use-module (gnu packages maths) + #:use-module (gnu packages perl) #:use-module (gnu packages pkg-config) #:use-module (gnu packages python) #:use-module (gnu packages python-build) #:use-module (gnu packages python-check) #:use-module (gnu packages python-xyz) #:use-module (gnu packages qt) + #:use-module (gnu packages readline) + #:use-module (gnu packages ruby) #:use-module (gnu packages sdl) #:use-module (gnu packages serialization) + #:use-module (gnu packages sphinx) #:use-module (gnu packages sqlite) #:use-module (gnu packages stb) #:use-module (gnu packages swig) + #:use-module (gnu packages texinfo) + #:use-module (gnu packages textutils) #:use-module (gnu packages tcl) #:use-module (gnu packages tls) #:use-module (gnu packages toolkits) #:use-module (gnu packages version-control) + #:use-module (gnu packages web) + #:use-module (gnu packages xdisorg) #:use-module (gnu packages xorg) #:use-module (gnu packages xml)) +(define-public aacircuit + ;; No release in PyPI or version tag on Git, use the latest commit. + (let ((commit "18635c846754b6219da1a2ceb8977714f70004d0") + (revision "0")) + (package + (name "aacircuit") + (version (git-version "0" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/Blokkendoos/AACircuit") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "07agb7fbpbq74zm27j9b00imr46q6kpwhxzmmffw2s9scv80c1km")))) + (build-system pyproject-build-system) + (arguments + (list + #:imported-modules `((guix build glib-or-gtk-build-system) + ,@%pyproject-build-system-modules) + #:modules '(((guix build glib-or-gtk-build-system) + #:prefix glib-or-gtk:) + (guix build pyproject-build-system) + (guix build utils)) + #:phases + #~(modify-phases %standard-phases + (add-after 'unpack 'generate-gdk-pixbuf-loaders-cache-file + (assoc-ref glib-or-gtk:%standard-phases + 'generate-gdk-pixbuf-loaders-cache-file)) + (replace 'check + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + ;; Delete develompent test file. + (delete-file "tests/test_flake.py") + ;; Exclude tests intended for visual review. + (setenv "NOSE_EXCLUDE" + (string-join '("test_export_pdf" + "test_import_aacircuit_export_pdf") + ",")) + (setenv "HOME" "/tmp") + (invoke "xvfb-run" "./testrunner.sh")))) + (add-after 'wrap 'glib-or-gtk-wrap + (assoc-ref glib-or-gtk:%standard-phases + 'glib-or-gtk-wrap)) + (add-after 'glib-or-gtk-wrap 'wrap-aacircuit + (lambda* (#:key outputs #:allow-other-keys) + (wrap-program (string-append (assoc-ref outputs "out") + "/bin/aacircuit") + `("GDK_PIXBUF_MODULE_FILE" = + (,(getenv "GDK_PIXBUF_MODULE_FILE"))) + `("GI_TYPELIB_PATH" ":" prefix + (,(getenv "GI_TYPELIB_PATH"))))))))) + (native-inputs + ;; XXX: Test runner may be migrated to Pytest + ;; <https://docs.pytest.org/en/7.1.x/how-to/nose.html> after report to + ;; the upstream to modify them, use deprecated Nose test runner for + ;; now. + (list python-nose + python-setuptools + python-wheel + xvfb-run)) + (inputs + (list bash-minimal + gtk+ + python-bresenham + python-platformdirs + python-pycairo + python-pyclip + python-pygobject + python-pypubsub)) + (home-page "https://github.com/Blokkendoos/AACircuit") + (synopsis "Draw electronic circuits with ASCII characters") + (description + "This is a pythonized, kind of reverse engineered version of original +AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout +are also taken from the original.") + (license license:gpl3+)))) + +(define-public abc + (let ((commit "c8eac7595d094dd45402133497d645fb74e545f0") + (revision "7")) + (package + (name "abc") + (version (git-version "0.0" revision commit)) + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/berkeley-abc/abc") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "14k2j54fwr2a3nmb637fclzdf22a16jw5fsmhr3cf42yd924yn71")))) + (build-system gnu-build-system) + (inputs + (list readline)) + (arguments + (list #:license-file-regexp "copyright.txt" + #:tests? #f ; no tests + #:phases + #~(modify-phases %standard-phases + (delete 'configure) + (replace 'install + (lambda _ + (install-file "abc" (string-append #$output "/bin"))))))) + (home-page "https://people.eecs.berkeley.edu/~alanmi/abc/") + (synopsis "Sequential logic synthesis and formal verification") + (description "ABC is a program for sequential logic synthesis and +formal verification.") + (license + (license:non-copyleft + "https://people.eecs.berkeley.edu/~alanmi/abc/copyright.htm"))))) + +(define-public abc-yosyshq + (package + (inherit abc) + (name "abc-yosyshq") + (version "0.58") + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/YosysHQ/abc/") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "191hsznsmsjn8100n50qsh3ng8wgrnyfhr7qcnb8yskiwqp37pjh")))) + (home-page "https://github.com/YosysHQ/abc/") + (description "ABC is a program for sequential logic synthesis and +formal verification. This is the Yosyshq fork of ABC.") + (license (license:non-copyleft "file:///copyright.txt")))) + +(define-public apycula + (package + (name "apycula") + (version "0.27") + ;; The pypi tar.gz file includes the necessary .pickle files, not available + ;; in the home-page repository. + (source + (origin + (method url-fetch) + (uri (pypi-uri "apycula" version)) + (sha256 + (base32 "15ndyjfpikn1hhgwp2l43pzlnjg3jg7zc86zr6vk5qr6jxpzm6j1")))) + (build-system pyproject-build-system) + (arguments (list #:tests? #f)) ;requires Gowin EDA tools + (inputs (list python-crc)) + (native-inputs (list python-setuptools python-wheel)) + (home-page "https://github.com/YosysHQ/apicula/") + (synopsis "Gowin FPGA bitstream format") + (description + "The project Apycula provides tools to support development and +generating bitstreams with Gowin FPGAs.") + (license license:expat))) + +(define-public camv-rnd + (package + (name "camv-rnd") + (version "1.1.6") + (source + (origin + (method url-fetch) + (uri (string-append "http://repo.hu/projects/camv-rnd/" + "releases/camv-rnd-" version ".tar.gz")) + (sha256 + (base32 + "1dp1vj5rpxlddx40paa9i727c92is3bz6z6pa0y6dy2nsjcm86fs")))) + (build-system glib-or-gtk-build-system) + (arguments + (list + #:tests? #f + #:phases + #~(modify-phases %standard-phases + (replace 'configure + ;; The configure script doesn't tolerate most of our configure + ;; flags. + (lambda _ + (setenv "CC" #$(cc-for-target)) + (setenv "LIBRND_PREFIX" #$(this-package-input "librnd")) + (invoke "./configure" (string-append "--prefix=" #$output))))))) + (inputs (list librnd)) + (home-page "http://repo.hu/projects/route-rnd/") + (synopsis "Viewer for electronic boards in CAM file formats") + (description + "@code{Camv-rnd} is a viewer for @acronym{PCB, Printed Circuit Board} +supporting gerber, excellon and g-code. It is part of the RiNgDove EDA +suite.") + (license license:gpl2+))) + (define-public comedilib (package (name "comedilib") @@ -106,7 +329,298 @@ individual low-level driver modules.") (home-page "https://www.comedi.org/") (license license:lgpl2.1))) -(define-public librnd +(define-public ieee-p1076 + (package + (name "ieee-p1076") + (version "2019") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://opensource.ieee.org/vasg/Packages/") + (commit (string-append "1076-" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1va626i5ww2ziw3dghw0d2mq7mrj5dwcn0h019h77866yw2pq9xn")))) + (build-system copy-build-system) + (native-inputs (list python-minimal-wrapper nvc python-vunit)) + (arguments + (list + ;; Not all 2019 features are supported by nvc compiler. + ;; pass 1055 of 1648 + #:tests? #f + #:install-plan + #~'(("ieee" "share/ieee/p1076/ieee" #:include ("vhdl")) + ("std" "share/ieee/p1076/std" #:include ("vhdl"))))) + (native-search-paths + (list (search-path-specification + (variable "IEEE-1076") + (separator #f) + (files (list "share/ieee/p1076"))))) + (home-page "https://IEEE-P1076.gitlab.io") + (synopsis "VHDL libraries corresponding to the IEEE 1076 standard") + (description + "Open source materials intended for reference by the IEEE standard 1076, +as approved and published by the @acronym{VHDL, Very High Speed Hardware +Description Language} Analysis and Standardization Group.") + (license license:asl2.0))) + +(define-public fftgen + (let ((commit "3378b77d83a98b06184656a5cb9b54e50dfe4485") ;no releases + (revision "1")) + (package + (name "fftgen") + (version (git-version "0" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/ZipCPU/dblclockfft") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1rvln871wjkbbqnv88jnx328xlhn5sgbr8fglk3ajnd9rwgiq3jg")))) + (build-system gnu-build-system) + (arguments + (list + #:test-target "bench-test" + #:make-flags #~(list "CFLAGS=-g -O2") ;default flags lack -O2 + #:phases + #~(modify-phases %standard-phases + (delete 'configure) + (replace 'install + (lambda _ + (install-file "sw/fftgen" + (string-append #$output "/bin"))))))) + (native-inputs (list bc fftw python-minimal verilator which)) + (synopsis "Generic pipelined FFT core generator") + (description "fftgen produces @acronym{FFT, fast-Fourier transforms} +hardware designs in Verilog.") + (home-page "https://github.com/ZipCPU/zipcpu/") + (license license:lgpl3+)))) + +(define-public gtkwave + ;; The last release is more than 2 years old, and there are improvements in + ;; the master branch, such as GTK 4 support: pick the latest commit that + ;; passes their CI. + (let ((commit "bb978d9d667d569b9153ffa34007e300302907dc") + (revision "0")) + (package + (name "gtkwave") + ;; The version string can be found in meson.build. + (version (git-version "3.4.0" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/gtkwave/gtkwave") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1nv27cpz5937cb6bkhpw8w0ji6hm9xr8f0znvfwzfl1fwwypf23y")))) + (build-system meson-build-system) + (arguments (list #:glib-or-gtk? #t)) + (native-inputs (list desktop-file-utils + flex + `(,glib "bin") ;for glib-mkenums + gobject-introspection + gperf + `(,gtk "bin") + pkg-config)) + (inputs (list gtk gtk+ libfst)) + (synopsis "Waveform viewer for FPGA simulator trace files") + (description "This package is a waveform viewer for @acronym{FST, FPGA +Simulator Trace} files.") + (home-page "https://github.com/gtkwave/gtkwave") + ;; Exception against free government use in tcl_np.c and tcl_np.h. + (license (list license:gpl2+ license:expat license:tcl/tk))))) + +(define-public iverilog + (package + (name "iverilog") + (version "12.0") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/steveicarus/iverilog") + (commit + (string-append "v" (string-replace-substring version "." "_"))))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17")))) + (build-system gnu-build-system) + (arguments + (list + #:bootstrap-scripts #~(list "autoconf.sh") + #:phases #~(modify-phases %standard-phases + (add-after 'unpack 'ensure-native-baked-CC/CXX + (lambda _ + ;; The compilers used to build are retained in + ;; bin/iverilog-vpi, which is a Makefile + ;; script. Normalize these to just 'gcc' and 'g++' to + ;; avoid having these set to cross compilers. + (substitute* "Makefile.in" + (("s;@IVCC@;\\$\\(CC);") + "s;@IVCC@;gcc;") + (("s;@IVCXX@;\\$\\(CXX);") + "s;@IVCXX@;g++;"))))))) + (native-inputs (list autoconf bison flex gperf)) + (inputs (list zlib)) + (home-page "https://steveicarus.github.io/iverilog/") + (synopsis "FPGA Verilog simulation and synthesis tool") + (description + "Icarus Verilog is a Verilog simulation and synthesis tool. +It operates as a compiler, compiling source code written in Verilog +(IEEE-1364) into some target format. +For batch simulation, the compiler can generate an intermediate form +called vvp assembly. +This intermediate form is executed by @command{vvp}. +For synthesis, the compiler generates netlists in the desired format.") + ;; GPL2 only because of: + ;; - ./driver/iverilog.man.in + ;; - ./iverilog-vpi.man.in + ;; - ./tgt-fpga/iverilog-fpga.man + ;; - ./vvp/vvp.man.in + ;; Otherwise would be GPL2+. + ;; You have to accept both GPL2 and LGPL2.1+. + (license (list license:gpl2 license:lgpl2.1+)))) + +(define-public icestorm + (package + (name "icestorm") + (version "1.1") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/YosysHQ/icestorm/") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 "0yh36kd23y4sk65g34r1h244ax9fj5c668y6pwqwaq3c0nmb3d28")))) + (build-system gnu-build-system) + (arguments + (list + #:tests? #f ;no tests + #:make-flags + #~(list (string-append "CC=" #$(cc-for-target)) + (string-append "CXX=" #$(cxx-for-target)) + (string-append "PREFIX=" #$output) + "ICEPROG=1") + #:phases + #~(modify-phases %standard-phases + (add-after 'unpack 'fix-usr-local + (lambda _ + (substitute* "config.mk" + (("/usr/local") + #$output)) + (substitute* "icepack/Makefile" + (("/usr/local") + #$output)) + (substitute* "icebox/Makefile" + (("/usr/local") + #$output)) + (substitute* "icebox/icebox_vlog.py" + (("/usr/local") + #$output)))) + (add-after 'build 'make-info + (lambda _ + (with-directory-excursion "docs" + (invoke "make" "info") + (install-file "build/texinfo/projecticestorm.info" + (string-append #$output "/share/info")) + (copy-recursively + "build/texinfo/projecticestorm-figures" + (string-append #$output + "/share/info/projecticestorm-figures"))))) + (delete 'configure)))) + (inputs + (list libftdi)) + (native-inputs + (list pkg-config + python-minimal + python-sphinx-rtd-theme + python-sphinxcontrib-svg2pdfconverter + texinfo)) + (home-page "https://prjicestorm.readthedocs.io/") + (synopsis "Bitstream tools for Lattice iCE40 FPGAs") + (description + "Project IceStorm aims at documenting the bitstream format of Lattice +iCE40 FPGAs and providing simple tools for analyzing and creating bitstream +files.") + (license license:isc))) + +(define-public json-for-vhdl + ;; No tagged releases. + (let ((commit "0dc9e317440263cd4941f157f5e5668baa858ec2") + (revision "0")) + (package + (name "json-for-vhdl") + (version (git-version "20220905" revision commit)) ;last revision + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/Paebbels/JSON-for-VHDL/") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1062g2c3dpsb67zhqrn1j04p7jl28g4mcxd6nhrqqfffjsvxkpw9")))) + (build-system copy-build-system) + (arguments + (list + #:install-plan + #~'(("src" "share/json-for-vhdl" + #:include ("vhdl"))) + #:phases + #~(modify-phases %standard-phases + ;; The examples/Encodings_VUnit test requires vhdl builtins. + (add-after 'unpack 'fix-check + (lambda _ + (substitute* "tests/VUnit/run.py" + (("from_argv\\(\\)") + "from_argv()\nvu.add_vhdl_builtins()")))) + (add-after 'install 'check + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + (invoke "python3" "tests/VUnit/run.py" "-v"))))))) + (native-inputs + (list nvc python-minimal python-vunit)) + (home-page "https://github.com/Paebbels/JSON-for-VHDL/") + (synopsis "Parse and query JSON data structures in VHDL") + (description + "The JSON-for-VHDL library provides a parser to query JSON data +structures from external files on disk. It provides a context to be +used in the declarative section of design units.") + (license license:asl2.0)))) + +;;; Required by python-vunit. +(define json-for-vhdl-for-vunit + (let ((commit "95e848b8902c6b4275d715462e1a2cc60706917c") ;sync with vunit + (revision "0")) + (package + (inherit json-for-vhdl) + (name "json-for-vhdl-for-vunit") + (version (git-version "20220106" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/Paebbels/JSON-for-VHDL/") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1c106hm0sfnzdi5j9vaacjlz7i5m1dm75j7lrgcdsa4siw5ac7k3")))) + (arguments + (list + #:install-plan + #~'(("src" "share/json-for-vhdl" #:include ("vhdl"))))) + (native-inputs + '())))) + +(define librnd (package (name "librnd") (version "4.3.2") @@ -144,6 +658,33 @@ individual low-level driver modules.") @end itemize") (license license:gpl2+))) +(define-public libfst + ;; There are no release nor tags. + (let ((commit "6a52070cd62ec65c29832bc95e7db493504aa7ac") + (revision "0")) + (package + (name "libfst") + (version (git-version "1.0.0" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/gtkwave/libfst/") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "0b1r660m5aib316jjl4nhs10y7vhhqy2mvxjip3ynahig3hpi46z")))) + (build-system meson-build-system) + (native-inputs (list gobject-introspection pkg-config)) + (inputs (list bzip2)) + (propagated-inputs (list zlib)) ;in Requires.private of libfst.pc + (synopsis "Fast Signal Trace (FST) format waveforms library") + (description "Libfst is a small library used to read and write +@acronym{FST, Fast Signal Trace} format waveforms.") + (home-page "https://github.com/gtkwave/libfst/") + (license (list license:expat ;libfst and fastlz-derived sources + license:bsd-2))))) ;for lz4-derived sources + (define-public libserialport (package (name "libserialport") @@ -182,39 +723,40 @@ to take care of the OS-specific details when writing software that uses serial p (file-name (git-file-name name version)))) (outputs '("out" "doc")) (arguments - `(#:tests? #f ; tests need USB access - #:phases - (modify-phases %standard-phases - (add-before 'configure 'change-udev-group - (lambda _ - (substitute* (find-files "contrib" "\\.rules$") - (("plugdev") "dialout")))) - (add-after 'build 'build-doc - (lambda _ - (invoke "doxygen"))) - (add-after 'install 'install-doc - (lambda* (#:key outputs #:allow-other-keys) - (copy-recursively "doxy/html-api" - (string-append (assoc-ref outputs "doc") - "/share/doc/libsigrok")))) - (add-after 'install-doc 'install-udev-rules - (lambda* (#:key outputs #:allow-other-keys) - (let* ((out (assoc-ref outputs "out")) - (rules (string-append out "/lib/udev/rules.d/"))) - (for-each (lambda (file) - (install-file file rules)) - (find-files "contrib" "\\.rules$"))))) - (add-after 'install-udev-rules 'install-fw - (lambda* (#:key inputs outputs #:allow-other-keys) - (let* ((fx2lafw (assoc-ref inputs "sigrok-firmware-fx2lafw")) - (out (assoc-ref outputs "out")) - (dir-suffix "/share/sigrok-firmware/") - (input-dir (string-append fx2lafw dir-suffix)) - (output-dir (string-append out dir-suffix))) - (for-each - (lambda (file) - (install-file file output-dir)) - (find-files input-dir ".")))))))) + (list + #:tests? #f ; tests need USB access + #:phases + #~(modify-phases %standard-phases + (add-before 'configure 'change-udev-group + (lambda _ + (substitute* (find-files "contrib" "\\.rules$") + (("plugdev") "dialout")))) + (add-after 'build 'build-doc + (lambda _ + (invoke "doxygen"))) + (add-after 'install 'install-doc + (lambda _ + (copy-recursively + "doxy/html-api" + (string-append #$output:doc "/share/doc/libsigrok")))) + (add-after 'install-doc 'install-udev-rules + (lambda _ + (for-each + (lambda (file) + (install-file + file + (string-append #$output "/lib/udev/rules.d/"))) + (find-files "contrib" "\\.rules$")))) + (add-after 'install-udev-rules 'install-fw + (lambda* (#:key inputs outputs #:allow-other-keys) + (let* ((fx2lafw (assoc-ref inputs "sigrok-firmware-fx2lafw")) + (dir-suffix "/share/sigrok-firmware/") + (input-dir (string-append fx2lafw dir-suffix)) + (output-dir (string-append #$output dir-suffix))) + (for-each + (lambda (file) + (install-file file output-dir)) + (find-files input-dir ".")))))))) (native-inputs (list autoconf automake doxygen graphviz libtool sigrok-firmware-fx2lafw pkg-config)) @@ -255,18 +797,18 @@ supported devices, as well as input/output file format support.") "11l8vnf2khqbaqas7cfnq3f8q5w7am6nbkkd5mqj5kpb3ya2avb9")))) (outputs '("out" "doc")) (arguments - `(#:phases - (modify-phases %standard-phases - (add-after 'build 'build-doc - (lambda _ - (invoke "doxygen") - #t)) - (add-after 'install 'install-doc - (lambda* (#:key outputs #:allow-other-keys) - (copy-recursively "doxy/html-api" - (string-append (assoc-ref outputs "doc") - "/share/doc/libsigrokdecode")) - #t))))) + (list + #:phases + #~(modify-phases %standard-phases + (add-after 'build 'build-doc + (lambda _ + (invoke "doxygen"))) + (add-after 'install 'install-doc + (lambda _ + (copy-recursively + "doxy/html-api" + (string-append #$output:doc + "/share/doc/libsigrokdecode"))))))) (native-inputs (list check doxygen graphviz pkg-config automake autoconf libtool)) ;; libsigrokdecode.pc lists "python" in Requires.private, and "glib" in @@ -285,7 +827,7 @@ supported devices, as well as input/output file format support.") (define-public m8c (package (name "m8c") - (version "1.7.10") + (version "2.2.0") (source (origin (method git-fetch) @@ -294,18 +836,17 @@ supported devices, as well as input/output file format support.") (commit (string-append "v" version)))) (file-name (git-file-name name version)) (sha256 - (base32 "18bx6jf0jbgnd6cfydh4iknh25rrpyc8awma4a1hkia57fyjy2gi")))) - (build-system gnu-build-system) + (base32 "1mx4n5di1bsm4ill55sf4dfa5rldrch0mrr4mk83x0xqd2rfy2mp")))) + (build-system cmake-build-system) (arguments (list - #:make-flags #~(list (string-append "PREFIX=" #$output)) - #:phases - #~(modify-phases %standard-phases - (delete 'configure)) - #:tests? #f)) ;no tests - (native-inputs (list pkg-config)) - (inputs (list libserialport - sdl2)) + #:tests? #f ;no tests + #:configure-flags + #~(list "-DUSE_LIBSERIALPORT=ON"))) + (native-inputs + (list pkg-config)) + (inputs + (list libdecor libserialport sdl3)) (home-page "https://github.com/laamaa/m8c") (synopsis "Cross-platform M8 tracker headless client") (description @@ -322,61 +863,212 @@ which allows one to install the M8 firmware on any Teensy.") license:public-domain license:zlib)))) -(define-public minipro - ;; When built from a Git repo, minipro expects GIT_DATE to be set to the - ;; value of `git show -s --format=%ci'. When updating the package, run this - ;; in a checkout and put the value here. - (let* ((date "2025-04-13 21:54:38 -0700")) +(define-public nextpnr + (let ((commit "ad76625d4d828cb093b55aa9f5aae59b7ba9724f") + (revision "0")) (package - (name "minipro") - (version "0.7.3") + (name "nextpnr") + (version (git-version "0.9" revision commit)) (source (origin (method git-fetch) (uri (git-reference - (url "https://gitlab.com/DavidGriffith/minipro.git") - (commit version))) + (url "https://github.com/YosysHQ/nextpnr/") + (commit commit) + ;; XXX: Fetch some bundled libraries such as QtPropertyBrowser, + ;; json11 and python-console, which have custom modifications or + ;; no longer have their original upstream. + (recursive? #t))) (file-name (git-file-name name version)) + (modules '((guix build utils) + (ice-9 ftw) + (srfi srfi-26))) + (snippet + '(begin + ;; XXX: 'delete-all-but' is copied from the turbovnc package. + (define (delete-all-but directory . preserve) + (with-directory-excursion directory + (let* ((pred (negate (cut member <> + (cons* "." ".." preserve)))) + (items (scandir "." pred))) + (for-each (cut delete-file-recursively <>) items)))) + (delete-all-but "3rdparty" + ;; The following sources have all been patched, so + ;; cannot easily be unbundled. + "QtPropertyBrowser" + "json11" + "python-console" + "oourafft"))) + (patches (search-patches "nextpnr-gtest.patch" + "nextpnr-imgui.patch")) (sha256 - (base32 "1525rn5h73xism16vmivd3cz93g8w76h24f0yvbpc35ydc3fkqf7")))) - (native-inputs (list pkg-config which)) - (inputs (list libusb zlib)) - (build-system gnu-build-system) + (base32 "1zjxvkycg5xx605d4ark8gd10w4xni1wd10chmhv983dvyv875br")))) + (outputs '("out" "bba")) + (build-system qt-build-system) (arguments (list - #:tests? #f ; no test suite + #:configure-flags + #~(list "-DARCH=generic;ice40;ecp5;himbaechel" + "-DBUILD_GUI=ON" + "-DUSE_OPENMP=ON" + "-DBUILD_TESTS=ON" + "-DHIMBAECHEL_UARCH=ng-ultra;gowin;gatemate" + "-DHIMBAECHEL_NGULTRA_DEVICES=ng-ultra" + "-DHIMBAECHEL_SPLIT=ON" + (string-append "-DHIMBAECHEL_PRJBEYOND_DB=" + (search-input-directory + %build-inputs "share/prjbeyond-db")) + (string-append "-DHIMBAECHEL_PEPPERCORN_PATH=" + (search-input-directory + %build-inputs "share/prjpeppercorn")) + (string-append + "-DEXPORT_BBA_FILES=" #$output:bba "/share/nextpnr/bba-files") + (string-append "-DCURRENT_GIT_VERSION=nextpnr-" #$version) + (string-append "-DICESTORM_INSTALL_PREFIX=" + #$(this-package-native-input "icestorm")) + (string-append "-DTRELLIS_INSTALL_PREFIX=" + #$(this-package-native-input "prjtrellis"))) #:phases #~(modify-phases %standard-phases - (delete 'configure) ; No ./configure script - (add-before 'build 'fix-makefile + (add-after 'unpack 'unbundle-sanitizers-cmake (lambda _ - ;; Fix some git related variables that minipro expects - (substitute* "Makefile" - (("GIT_BRANCH = .*") - (string-append "GIT_BRANCH = \"master\"\n")) - (("GIT_HASH = .*") - (string-append "GIT_HASH = \"" #$version "\"\n")) - (("GIT_DATE = .*") - (string-append "GIT_DATE = \"" #$date "\"\n")))))) - #:make-flags - #~(list (string-append "VERSION=" #$version) - (string-append "PREFIX=" #$output) - (string-append "UDEV_DIR=" #$output "/lib/udev") - (string-append "COMPLETIONS_DIR=" #$output - "/share/bash-completion/completions")))) - (synopsis "Controls the TL866xx series of chip programmers") - (description - "minipro is designed to program or read the contents of -chips supported by the TL866xx series of programmers. This includes many -microcontrollers, ROMs, EEPROMs and PLDs. + (substitute* "CMakeLists.txt" + ;; Use the system sanitizers-cmake module. This is made + ;; necessary 'sanitizers-cmake' installing a FindPackage + ;; module but no CMake config file. + (("\\$\\{CMAKE_SOURCE_DIR}/3rdparty/sanitizers-cmake/cmake") + (string-append + #$(this-package-native-input "sanitizers-cmake") + "/share/sanitizers-cmake/cmake"))))) + (add-after 'install 'run-tests + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + (setenv "PATH" + (string-append #$output "/bin:" (getenv "PATH"))) + ;; ice40 + (invoke "./nextpnr-ice40-test") + (chdir "../source") + (setenv "NEXTPNR" "nextpnr-ice40") + (with-directory-excursion "ice40/smoketest/attosoc" + (invoke "./smoketest.sh")) + (with-directory-excursion "tests/ice40/regressions" + (invoke "make" (string-append + "NPNR=" #$output "/bin/nextpnr-ice40"))) + ;; generic + (setenv "NPNR" "nextpnr-generic") + (invoke "nextpnr-generic" "--uarch" "example" "--test") + (with-directory-excursion "tests/generic/flow/bel-pin" + (invoke "./run.sh")) + ;; ecp5 + (invoke "nextpnr-ecp5" + "--um5g-25k" "--package" "CABGA381" "--test") + (with-directory-excursion "tests/ecp5/regressions" + (invoke "make" + (string-append + "NPNR=" #$output "/bin/nextpnr-ecp5"))))))))) + (native-inputs + (list icestorm + iverilog + googletest + gzip + prjbeyond-db + `(,prjpeppercorn "db") + prjtrellis + sanitizers-cmake + yosys)) + (inputs + (list apycula + boost + corrosion + eigen + pybind11 + python + qtbase-5 + qtwayland-5 + qtimgui)) + (synopsis "Place-and-Route tool for FPGAs") + (description "Nextpnr is a portable FPGA place and route tool.") + (home-page "https://github.com/YosysHQ/nextpnr/") + (license license:isc)))) -To use this program without root privileges you must install the necessary udev -rules. This can be done by extending @code{udev-service-type} in your -@code{operating-system} configuration with this package. E.g.: -@code{(udev-rules-service 'minipro minipro #:groups '(\"plugdev\")}. -Additionally your user must be member of the @code{plugdev} group.") - (home-page "https://gitlab.com/DavidGriffith/minipro") - (license license:gpl3+)))) +(define-public nextpnr-cli + (package + (inherit nextpnr) + (name "nextpnr-cli") + (build-system cmake-build-system) + (arguments + (substitute-keyword-arguments (package-arguments nextpnr) + ((#:configure-flags flags '()) + #~(delete! "-DBUILD_GUI=ON" #$flags)))) + (inputs + (modify-inputs (package-inputs nextpnr) + (delete "qtbase-5" "qtwayland-5" "qtimgui"))) + (synopsis + (string-append (package-synopsis nextpnr) " Cli only version.")))) + +(define-public nextpnr-ice40 + (deprecated-package "nextpnr-ice40" nextpnr)) + +(define-public nvc + (package + (name "nvc") + (version "1.18.0") + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/nickg/nvc") + (commit (string-append "r" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1b8bsmxv2p9v8g7yzdj8s22l5bx9n58kmbklgnj17gd362lai51y")))) + (build-system gnu-build-system) + (arguments + (list #:out-of-source? #t + #:configure-flags + #~(list "--enable-tcl" + "--enable-llvm" + "--enable-verilog" + "--enable-vital" + "--enable-server" + "--with-ncurses" + "--enable-parallel-make" + "--enable-vital" + (string-append "--with-bash-completion=" #$output + "/share/bash-completion/completions")) + #:phases #~(modify-phases %standard-phases + (add-after 'unpack 'fix-autogen + (lambda _ + (substitute* "autogen.sh" + (("cd") "# cd")))) + ;; This scripts is necessary for testing osvvm. + (add-after 'install 'keep-osvvm-tests + (lambda _ + (mkdir-p (string-append #$output "/test")) + (install-file + "../source/test/test-osvvm.tcl" + (string-append #$output "/test"))))))) + (native-inputs + (list automake + autoconf + check ; for the tests + flex + gettext-minimal + libtool + pkg-config + python-minimal + which)) + (inputs + (list jansson + libffi + llvm + readline + tcl + `(,zstd "lib"))) + (synopsis "VHDL compiler and simulator") + (description "This package provides a VHDL compiler and simulator.") + (home-page "https://www.nickg.me.uk/nvc/") + (license license:gpl3+))) (define-public openboardview (package @@ -502,10 +1194,86 @@ such as: editor, part of the RiNgDove EDA suite.") (license license:gpl2+))) +(define prjbeyond-db + ;; Projects doesn’t include any tag or release. + (let ((commit "f49f66be674d9857c657930353b867ba94bcbdd7") + (revision "0")) + (package + (name "prjbeyond-db") + (version (git-version "0" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/yosyshq-GmbH/prjbeyond-db/") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1q5dfg0s21q8aw63fz28h0av958g0vcgi179yacgvs9f0cm6dx87")))) + (build-system copy-build-system) + (arguments + (list + #:install-plan + #~'(("NG-ULTRA" "share/prjbeyond-db/") + ("devices.json" "share/prjbeyond-db/")))) + (home-page "https://github.com/yosyshq-GmbH/prjbeyond-db/") + (synopsis "Chip database for FPGA NG-Ultra architecture") + (description "This package includes data needed to create @code{nextpnr} +chip database for NG-Ultra architecture from NanoXplore.") + (license license:expat)))) + +(define-public prjpeppercorn + (package + (name "prjpeppercorn") + (version "1.8") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/YosysHQ/prjpeppercorn/") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1lfvd3r1pnyc1mxsiiqqvmp8r5pw1bshgjrsrsnd20grvlv6wwcn")))) + + (outputs (list "out" + "db")) ;FPGA database files + (build-system cmake-build-system) + (arguments + (list + #:tests? #f ;no test suite + #:configure-flags + #~(list "-DBUILD_SHARED=ON" + "-DSTATIC_BUILD=OFF") + #:phases + #~(modify-phases %standard-phases + (add-after 'unpack 'chdir + (lambda _ + (chdir "libgm"))) + (add-before 'chdir 'install-db-files + (lambda _ + (let ((datadir + (string-append #$output:db "/share/prjpeppercorn"))) + (mkdir-p datadir) + (copy-recursively "delay" (string-append datadir "/delay")) + (copy-recursively "gatemate" + (string-append datadir "/gatemate")) + (copy-recursively "tools" + (string-append datadir "/tools")))))))) + (inputs + (list boost)) + (synopsis "GateMate FPGAs bitstream tools") + (description + "@code{Prjpeppercorn} includes programming tools for GateMate +architecture from Cologne Chip. It also provides data needed to produce a +@code{nextpnr} chip database Cologne Chip's GateMate architecture.") + (home-page "https://github.com/YosysHQ/prjpeppercorn/") + (license license:isc))) + (define-public prjtrellis ;; The last release is 2 years old; use the latest commit for now. - (let ((commit "898329dddf6ce6463299973081f109d645b9c55f") - (revision "0")) + (let ((commit "92345b77edf775fe5668700dd9931e19db2d36b0") + (revision "1")) (package (name "prjtrellis") (version (git-version "1.4" revision commit)) @@ -526,7 +1294,7 @@ editor, part of the RiNgDove EDA suite.") (for-each delete-file-recursively '("pybind11")))) (sha256 - (base32 "1qljgn7rxz114vki21rms70zi9rgr4gw7crdfihxx1n68zgv60gg")))) + (base32 "1yl5qw846jbnwzs8jv8bllz0zrzsg8amphvl9nskq5p5fz188q22")))) (build-system cmake-build-system) (arguments (list @@ -561,12 +1329,12 @@ The following features are currently available: (define-public opensta ;; There are no releases, we use last commit. - (let ((commit "eb8d39a7dd81b5ca2582ad9bbce0fb6e094b3e0f") + (let ((commit "12f03395ec80d3593f4796b2a3cf5480e75735bd") (revision "0")) (package (name "opensta") ;; The version string is taken from the CMakeLists.txt. - (version (git-version "2.6.2" revision commit)) + (version (git-version "2.7.0" revision commit)) (source (origin (method git-fetch) @@ -575,20 +1343,27 @@ The following features are currently available: (commit commit))) (file-name (git-file-name name version)) (sha256 - (base32 "0bpc7fj4pd5713yny2vrh542jbag1kj20g0ji01c9scqb9av5qw5")))) + (base32 "1gka50p4wv2b49d8jbw5fs3qg7cppa8ynl3diqgdf8mqgskwapzf")))) (build-system cmake-build-system) (arguments (list + ;; Tests expect output sta binary inside source tree. + #:out-of-source? #f #:phases #~(modify-phases %standard-phases (replace 'check (lambda* (#:key tests? #:allow-other-keys) (when tests? - (invoke "../source/test/regression"))))) + (invoke "../test/regression")))) + (add-before 'build 'create-build-dir + (lambda _ + (mkdir-p "./build") + (chdir "./build")))) #:configure-flags #~(list (string-append "-DCUDD_DIR=" #$(this-package-input "cudd")) - (string-append "-DBUILD_SHARED_LIBS=YES")))) + (string-append "-DBUILD_SHARED_LIBS=YES") + "-B./build"))) (native-inputs (list bison flex swig)) (inputs (list cudd eigen tcl tcllib zlib)) (synopsis "Parallax Static Timing Analyzer") @@ -603,28 +1378,29 @@ formats.") (package (name "pulseview") (version "0.4.2") - (source (origin - (method url-fetch) - (uri (string-append - "https://sigrok.org/download/source/pulseview/pulseview-" - version ".tar.gz")) - (sha256 - (base32 - "1jxbpz1h3m1mgrxw74rnihj8vawgqdpf6c33cqqbyd8v7rxgfhph")) - (patches (search-patches "pulseview-qt515-compat.patch" - "pulseview-glib-2.68.patch")))) + (source + (origin + (method url-fetch) + (uri (string-append + "https://sigrok.org/download/source/pulseview/pulseview-" + version ".tar.gz")) + (sha256 + (base32 + "1jxbpz1h3m1mgrxw74rnihj8vawgqdpf6c33cqqbyd8v7rxgfhph")) + (patches (search-patches "pulseview-qt515-compat.patch" + "pulseview-glib-2.68.patch")))) (build-system cmake-build-system) (arguments - `(#:tests? #f ;format_time_minutes_test is failing - #:phases - (modify-phases %standard-phases - (add-after 'install 'remove-empty-doc-directory - (lambda* (#:key outputs #:allow-other-keys) - (let ((out (assoc-ref outputs "out"))) - (with-directory-excursion (string-append out "/share") - ;; Use RMDIR to never risk silently deleting files. - (rmdir "doc/pulseview") - (rmdir "doc")))))))) + (list + #:tests? #f ;format_time_minutes_test is failing + #:phases + #~(modify-phases %standard-phases + (add-after 'install 'remove-empty-doc-directory + (lambda _ + (with-directory-excursion (string-append #$output "/share") + ;; Use RMDIR to never risk silently deleting files. + (rmdir "doc/pulseview") + (rmdir "doc"))))))) (native-inputs (list pkg-config qttools-5)) (inputs @@ -637,14 +1413,115 @@ formats.") qtsvg-5)) (home-page "https://www.sigrok.org/wiki/PulseView") (synopsis "Qt based logic analyzer, oscilloscope and MSO GUI for sigrok") - (description "PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI -for sigrok.") + (description "PulseView is a Qt based logic analyzer, oscilloscope and MSO +GUI for sigrok.") (license license:gpl3+))) +(define-public osvvm + (package + (name "osvvm") + (version "2025.06a") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/osvvm/OsvvmLibraries/") + (commit version) + ;; OsvvmLibraries repository gathers all osvvm libraries as + ;; submodules. + (recursive? #t))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1dq56h51ydfpffd00qz9qkcg6sddlqixiixls9vvxczfkp9l21ws")))) + (outputs + '("out" "common" "scripts" "uart" "axi4")) + (properties + `((output-synopsis "out" "Verification Utility Library") + (output-synopsis "common" "Common library") + (output-synopsis "scripts" "Simulator script library") + (output-synopsis "uart" "UART Verification Component Library") + (output-synopsis "axi4" "AXI4 Verification Component Library"))) + (build-system copy-build-system) + (arguments + (list + #:install-plan + #~'(("osvvm" "share/osvvm/osvvm/" + #:include ("vhd" "pro" "md") + #:output "out") + ("Common" "share/osvvm/Common/" + #:include ("vhd" "pro" "md") + #:output "common") + ("Scripts" "share/osvvm/Scripts/" + #:include ("tcl" "md") + #:output "scripts") + ("UART" "share/osvvm/UART" + #:include ("vhd" "pro" "md") + #:exclude-regexp ("GHDL_Debug") + #:output "uart") + ("AXI4" "share/osvvm/AXI4" + #:include ("vhd" "pro" "md") + #:output "axi4")) + #:phases + #~(modify-phases %standard-phases + (add-before 'install 'fix-scripts + (lambda _ + ;; Default conflicts with read-only /gnu/store. + (substitute* "osvvm/OsvvmVhdlSettings.pro" + (("\\[FindOsvvmSettingsDirectory\\]") + " \"\" ")))) + (add-after 'fix-scripts 'check + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + (setenv "OSVVM_DIR" (getcwd)) + (setenv "OSVVM_MUST_BUILD" (getcwd)) + (invoke "tclsh" + (string-append #$(this-package-native-input "nvc") + "/test/test-osvvm.tcl")))))))) + (native-inputs + (list nvc tcl tcllib which)) + (native-search-paths + (list (search-path-specification + (variable "OSVVM") + (separator #f) + (files (list "share/osvvm"))))) + (home-page "https://osvvm.github.io/Overview/Osvvm1About.html/") + (synopsis "The OSVVM VHDL Verification Libraries and Scripts") + (description "OSVVM is a verification methodology that defines a VHDL +verification framework, verification utility library, verification component +library, scripting API, and co-simulation capability for FPGA or ASIC +verification.") + (license license:asl2.0))) + +;;; Required by python-vunit. +(define osvvm-2023.04 + (package + (inherit osvvm) + (name "osvvm") + (version "2023.04") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/osvvm/OsvvmLibraries/") + (commit version) + ;; OsvvmLibraries repository gathers all osvvm libraries as + ;; submodules. + (recursive? #t))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1kn18ibvm7bzdyw2d914284wriravyh5qwfarj06pb052x1yblyx")))) + (arguments + (substitute-keyword-arguments (package-arguments osvvm) + ((#:tests? _ #t) + #f) + ((#:phases phases #~%standard-phases) + #~(modify-phases #$phases + (delete 'fix-scripts))))))) + (define-public python-cocotb (package (name "python-cocotb") - (version "2.0.0b1") + (version "2.0.0") (source (origin (method git-fetch) @@ -653,7 +1530,7 @@ for sigrok.") (commit (string-append "v" version)))) (file-name (git-file-name name version)) (sha256 - (base32 "14aas4vw9cb9krnvw21vfmwqivvc2cwzi9rvmvap6xcw9f2dsyy9")))) + (base32 "0b9wc14df11wkwa20wkij4iip07841qsr0yir9g7dww069rj36q6")))) (build-system pyproject-build-system) (arguments (list @@ -663,8 +1540,7 @@ for sigrok.") (list iverilog nvc python-pytest - python-setuptools - python-wheel)) + python-setuptools)) (propagated-inputs (list python-find-libpython)) (home-page "https://github.com/cocotb/cocotb") @@ -677,10 +1553,11 @@ and Verilog RTL using Python.") (define-public python-cocotb-bus ;; XXX: The latest tagged release (2.6.1) was placed on <2023-07-01>, switch ;; to tag when the fresh release is available. - (let ((commit "8269cbdacdc26e676eace4e19fc753c96ac9a059") - (revision "0")) + (let ((commit "f5578a4d451ef6bc1efdd4919de5facdb381b781") + (revision "2")) (package (name "python-cocotb-bus") + ;; Version from src/cocotb_bus/_version.py (version (git-version "0.2.1" revision commit)) (source (origin @@ -690,7 +1567,7 @@ and Verilog RTL using Python.") (commit commit))) (file-name (git-file-name name version)) (sha256 - (base32 "12762rdg630dq5qyvnv1g9kc36g0997nx8c5qndl34v6s9fc2152")))) + (base32 "13zdqalzhzrfv1lcn6l71zhi4hns89y093hvz9swkcr2kzwfn08r")))) (build-system pyproject-build-system) ;; TODO: Build documentation from <docs>. (arguments @@ -706,8 +1583,7 @@ and Verilog RTL using Python.") (list iverilog nvc python-pytest - python-setuptools - python-wheel)) + python-setuptools)) (propagated-inputs (list python-cocotb python-packaging @@ -721,7 +1597,7 @@ and reusable bus interfaces to be used with @code{cocotb}.") (define-public python-edalize (package (name "python-edalize") - (version "0.6.0") + (version "0.6.1") (source (origin (method git-fetch) @@ -730,7 +1606,7 @@ and reusable bus interfaces to be used with @code{cocotb}.") (commit (string-append "v" version)))) (file-name (git-file-name name version)) (sha256 - (base32 "1gfysk6wj3mxndyzma604i3y2lkfn1im0bdmzxv5rn4x2nyk68sc")))) + (base32 "03mkzkmi96jkrpgcnawixvy832p3b8li8lrirdjhfp9dmp7d5kg5")))) (build-system pyproject-build-system) (arguments (list @@ -739,18 +1615,13 @@ and reusable bus interfaces to be used with @code{cocotb}.") ;; XXX: Tests failing with assertion not equal, find out ;; why. (list "not test_gatemate" - "test_gatemate_minimal" "test_vcs_tool_options" "test_vcs_no_tool_options" "test_vcs_minimal" - "test_vivado_edif_netlist" - "test_vivado_edif_netlist_no_link_design" "test_xcelium") " and not ")))) (native-inputs - (list python-pytest - python-setuptools - python-wheel)) + (list python-pytest python-setuptools)) (propagated-inputs (list python-jinja2)) (home-page "https://github.com/olofk/edalize/") @@ -765,6 +1636,119 @@ perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.") (license license:bsd-2))) +(define-public python-hdlmake + (package + (name "python-hdlmake") + (version "4.0") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://gitlab.com/ohwr/project/hdl-make/") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1mbsm1j058j3wjp0hypd7a9d1xh3xsmy9p3jl9xcpnzjmncm34xr")))) + (build-system pyproject-build-system) + (arguments + (list + #:phases #~(modify-phases %standard-phases + (add-before 'check 'chdir + (lambda _ + (chdir "testsuite"))) + (add-before 'chdir 'build-info + (lambda _ + (invoke "make" "-C" "docs" "info") + (install-file + "docs/_build/texinfo/hdlmake.info" + (string-append #$output "/share/info")) + (copy-recursively + "docs/_build/texinfo/hdlmake-figures" + (string-append + #$output "/share/info/hdlmake-figures"))))) + #:test-flags #~(list "test_all.py"))) + (native-inputs + (list python-pytest-cov + python-setuptools + python-sphinx + texinfo)) + (propagated-inputs (list python-networkx)) + (home-page "https://ohwr.gitlab.io/project/hdl-make/") + (synopsis "Generate multi-purpose makefiles for HDL projects") + (description + "Hdlmake helps manage and share @acronym{HDL, hardware description +language} code by automatically finding file dependencies, writing synthesis +and simulation Makefiles.") + (license license:gpl3+))) + +(define-public python-migen + ;; XXX: The latest version tag (0.9.2) was placed in 2019, there are latest + ;; changes supporting Python 3.11 on master branch, see + ;; <https://github.com/m-labs/migen/issues/259>. + (let ((commit "6e3a9e150fb006dabc4b55043d3af18dbfecd7e8") + (revision "1")) + (package + (name "python-migen") + (version (git-version "0.9.2" revision commit)) + (source + (origin + ;; Tests fail in the PyPI tarball due to missing files. + (method git-fetch) + (uri (git-reference + (url "https://github.com/m-labs/migen") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1hibhjnj5b3ka5y4nnqx9zp5w730gfqfa3r5injpa14i4cz6bj1n")))) + (build-system pyproject-build-system) + (native-inputs + (list python-pytest + python-setuptools)) + (propagated-inputs + (list python-colorama)) + (home-page "https://m-labs.hk/gateware/migen/") + (synopsis "Python toolbox for building complex digital hardware") + (description + "Migen FHDL is a Python library that replaces the event-driven paradigm +of Verilog and VHDL with the notions of combinatorial and synchronous +statements, has arithmetic rules that make integers always behave like +mathematical integers, and allows the design's logic to be constructed by a +Python program.") + (license license:bsd-2)))) + +(define-public python-myhdl + (let ((commit "7dc29c242cd33cb835c336a81ffc3a461eaa92f4") + (revision "0")) + (package + (name "python-myhdl") + (version (git-version "0.11" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/myhdl/myhdl/") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1b91yvr0ksrw3bx61i7914caf8pyks9c242kwmj4l12zjd06mp56")))) + (arguments + (list + #:phases + #~(modify-phases %standard-phases + (replace 'check + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + (invoke "make" "iverilog" "core"))))))) + (build-system pyproject-build-system) + (native-inputs + (list iverilog python-setuptools python-pytest)) + (home-page "http://www.myhdl.org/") + (synopsis "Python as a Hardware Description Language") + (description "This package provides a library to turn Python into +a hardware description and verification language.") + (license license:lgpl2.1+)))) + (define-public python-pydigitalwavetools (package (name "python-pydigitalwavetools") @@ -832,7 +1816,7 @@ design.") (define-public python-vsg (package (name "python-vsg") - (version "3.32.0") + (version "3.34.0") (source (origin (method git-fetch) @@ -841,14 +1825,15 @@ design.") (commit version))) (file-name (git-file-name name version)) (sha256 - (base32 "0ql96n291zm4j324q8fmlvy8xvrksb8v6fip0g0sw374z86hda53")))) + (base32 "0sryf1wv4r5maxj4di5rpsmzcxins3gq8aksv7cpw6ywvdk1nj5l")))) (build-system pyproject-build-system) (arguments (list #:test-flags ;; Tests are expensive and may introduce race condition on systems with ;; high (more than 16) threads count; limit parallel jobs to 8x. - #~(list "--numprocesses" (number->string (min 8 (parallel-job-count)))) + #~(list + "--numprocesses" (number->string (min 8 (parallel-job-count)))) #:phases #~(modify-phases %standard-phases (add-after 'unpack 'pathch-pytest-options @@ -858,10 +1843,10 @@ design.") ((".*--self-contained-html.*") "") ((".*-n.*auto.*") ""))))))) (native-inputs - (list python-pytest + (list python-pytest-cov + python-pytest-html python-pytest-xdist - python-setuptools - python-wheel)) + python-setuptools)) (propagated-inputs (list python-pyyaml)) (home-page "https://github.com/jeremiah-c-leary/vhdl-style-guide/") @@ -871,6 +1856,214 @@ design.") to enforce it.") (license license:gpl3+))) +(define-public python-vunit + (package + (name "python-vunit") + (version "5.0.0-dev.6") ;v4.7.0 dates back from 2 years ago. + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/VUnit/vunit") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1si542jrrvibiigaridg2vds5smbiass7g5pdfk5z26xqgbh0fxc")))) + (build-system pyproject-build-system) + (arguments + (list + #:modules '((guix build pyproject-build-system) + (guix build utils) + (ice-9 ftw) + (srfi srfi-26)) + #:phases + #~(modify-phases %standard-phases + (add-after 'unpack 'fix-ghdl-jit + (lambda _ + ;; TODO: Remove when fixed upstream (see: + ;; https://github.com/VUnit/vunit/pull/1121). + (substitute* "vunit/sim_if/ghdl.py" + ((": \"llvm\",") + (string-append + ": \"llvm\",\n\tr\"static elaboration, LLVM JIT code " + "generator\": \"llvm-jit\","))))) + (add-after 'install 'unbundle + (lambda* (#:key inputs outputs #:allow-other-keys) + (let ((site-packages + (string-append (site-packages inputs outputs) + "/vunit/vhdl/"))) + (mkdir-p (string-append site-packages "JSON-for-VHDL")) + (symlink + (search-input-directory inputs "share/json-for-vhdl") + (string-append site-packages "JSON-for-VHDL/src")) + (symlink + (search-input-directory inputs "share/osvvm/osvvm") + (string-append site-packages "osvvm"))))) + (add-after 'check 'run-examples + ;; Run examples as an extra check. + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + (with-directory-excursion "examples/vhdl" + (for-each + (lambda (dir) + (invoke "python3" (string-append dir "/run.py")) + (delete-file-recursively "vunit_out")) + (scandir "." + (negate + (cut member <> + '("coverage" ;unsupported feature in nvc + "data_types" ;no run.py + "docker_runall.sh" ;not a test + "vivado" ;requires external tool + ;; Fails with nvc + "array_axis_vcs" + "osvvm_log_integration" + "run" + "third_party_integration" + "user_guide" + "." "..")))))))))) + #:test-flags + ;; Skip lint tests which require python-pycodestyle, python-pylint and + ;; python-mypy to reduce closoure size; some lint test fails, see + ;; <https://github.com/VUnit/vunit/issues/1111>. + ;; + ;; XXX: Acceptance tests take 10+ minutes to complete, hang on + ;; "test_external_run_scripts.py" and fail eventually, consider to + ;; improve them; ignore for now. + #~(list "tests/unit"))) + (native-inputs + (list nvc + python-pytest + python-setuptools + python-setuptools-scm + python-wheel)) + (inputs + (list json-for-vhdl-for-vunit osvvm-2023.04)) + (propagated-inputs + (list python-colorama)) + (home-page "https://vunit.github.io") + (synopsis "Unit testing framework for VHDL/SystemVerilog") + (description + "VUnit features the functionality needed to realize continuous and +automated testing of HDL code.") + ;; According to 'LICENSE.rst', VUnit itself is under MPL but two + ;; subdirectories are under ASL. + (license (list license:mpl2.0 license:asl2.0)))) + +(define-public qucsator-rf + (package + (name "qucsator-rf") + (version "1.0.7") ;required by qucs-s, keep in sync + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/ra3xdh/qucsator_rf/") + (commit version))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1qyih418r0jcrpk1ja4p7v9v5iqvri8iszg7s3vaf1d2agwblzb4")))) + (build-system cmake-build-system) + (arguments + (list + #:tests? #f ;no tests + #:phases + #~(modify-phases %standard-phases + (add-after 'install 'run-tests + (lambda* (#:key tests? #:allow-other-keys) + (when tests? + ;; Qucs-test is a collection of python scripts and data test + ;; cases. Its purpose is to test Qucs (GUI) and Qucsator; + ;; tests are under `testsuite` directory. + (copy-recursively + #$(origin + (method git-fetch) + (uri + ;; Using latest revision; refer to + ;; .github/workflows/cmake.yml to keep up to date. + (git-reference + (url "https://github.com/ra3xdh/qucs-test/") + (commit "ce69e05ceecab910175e6ea36b6e021a6d279947"))) + (sha256 + (base32 + (string-append "1r3hx43wvd0s11mzsvj1chylzv" + "0lk9qhaw7205j9x316ly03bl08")))) + "qucs-test") + (with-directory-excursion "qucs-test" + (invoke "python3" "run.py" "--qucsator" + (format #f "--prefix=~a/bin" #$output) + "--exclude=skip.txt")))))) + #:configure-flags + #~(list (format #f "-DBISON_DIR=~a/bin" + #$(this-package-native-input "bison")) + (format #f "-DADMSXML_DIR=~a/bin" + #$(this-package-native-input "adms"))))) + (native-inputs + (list adms bison dos2unix flex gperf python python-looseversion + python-numpy python-matplotlib)) + (synopsis "RF and microwave circuits simulator") + (description + "@code{Qucsator-rf} is a command line driven circuit simulator targeted +for RF and microwave circuits. It takes a network list in a certain format as +input and outputs an XML dataset.") + (home-page "https://ra3xdh.github.io//") + (license license:gpl2+))) + +(define-public qucs-s + (package + (name "qucs-s") + (version "25.2.0") ;update qucsator-rf accordingly + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/ra3xdh/qucs_s") + (commit version))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "0328irynm8vy4xjdip5286fd8nag1zdp0p6rcbhdhp4fca6wp5ak")))) + (build-system qt-build-system) + (arguments + (list + #:qtbase qtbase ;for Qt 6 + #:tests? #f ;no tests + #:phases + #~(modify-phases %standard-phases + (add-after 'unpack 'adjust-default-settings + (lambda* (#:key inputs #:allow-other-keys) + (substitute* "qucs/settings.cpp" + (("\"ngspice\"") + (format #f "~s" (search-input-file inputs "bin/ngspice"))) + (("\"octave\"") + (format #f "~s" (search-input-file inputs "bin/octave")))))) + (add-after 'install 'wrap-program + (lambda _ + (wrap-program (string-append #$output "/bin/qucs-s") + `("PATH" ":" prefix + (,(string-append #$(this-package-input "ngspice") "/bin") + ,(string-append + #$(this-package-input "qucsator-rf") "/bin"))))))))) + (native-inputs (list qttools)) + (inputs + ;; TODO Add xyce-serial to the list. + (list bash-minimal octave qtbase qtcharts qtsvg qtwayland qucsator-rf ngspice)) + (synopsis "GUI for different circuit simulation kernels") + (description + "@acronym{Qucs-S, Quite universal circuit simulator with SPICE} provides +a fancy graphical user interface for a number of popular circuit simulation +engines. The package contains libraries for schematic capture, visualization +and components. The following simulation kernels are supported: +@itemize +@item Ngspice (recommended) +@item Xyce +@item SpiceOpus +@item Qucsator (non-SPICE) +@end itemize\n") + (home-page "https://ra3xdh.github.io/") + (license license:gpl2+))) + (define-public xschem (package (name "xschem") @@ -912,6 +2105,75 @@ netlists from the drawn schematic, allowing the simulation of the circuit.") (home-page "https://xschem.sourceforge.io/stefan/index.html") (license license:gpl2+))) +(define-public route-rnd + (package + (name "route-rnd") + (version "0.9.3") + (source + (origin + (method url-fetch) + (uri (string-append "http://repo.hu/projects/route-rnd/" + "releases/route-rnd-" version ".tar.gz")) + (sha256 + (base32 + "0fy3b48s72lpicyap3y6jr9fyvb2ri42jb0gqxk6s927a278bfhc")))) + (build-system gnu-build-system) + (arguments + (list + #:tests? #f + #:make-flags #~(list (string-append "PREFIX=" #$output)) + #:phases + #~(modify-phases %standard-phases + (replace 'configure + ;; The configure script doesn't tolerate most of our configure + ;; flags. + (lambda _ + (setenv "CC" #$(cc-for-target)) + (setenv "LIBRND_PREFIX" #$(this-package-input "librnd")) + (invoke "./configure" (string-append "--prefix=" #$output))))))) + (inputs (list librnd)) + (home-page "http://repo.hu/projects/route-rnd/") + (synopsis "Automatic routing for electronics boards") + (description + "@code{Route-rnd} is a generic external autorouter for @acronym{PCB, +Printed Circuit Board} using tEDAx file format, part of the RiNgDove EDA +suite.") + (license license:gpl2+))) + +(define-public sch-rnd + (package + (name "sch-rnd") + (version "1.0.9") + (source + (origin + (method url-fetch) + (uri (string-append "http://repo.hu/projects/sch-rnd/" + "releases/sch-rnd-" version ".tar.gz")) + (sha256 + (base32 + "07a1ik0rpsa5cscg9l7i5rnipx76543s7cdnkg802747rral7yj5")))) + (build-system glib-or-gtk-build-system) + (arguments + (list + #:test-target "test" + #:phases + #~(modify-phases %standard-phases + (replace 'configure + ;; The configure script doesn't tolerate most of our configure + ;; flags. + (lambda _ + (setenv "CC" #$(cc-for-target)) + (setenv "LIBRND_PREFIX" #$(this-package-input "librnd")) + (invoke "./configure" (string-append "--prefix=" #$output))))))) + (inputs (list librnd)) + (home-page "http://repo.hu/projects/sch-rnd/") + (synopsis "Scriptable editor of schematics for electronics boards") + (description + "@code{Sch-rnd} is a standalone and workflow agnostic schematics capture +tool for @acronym{PCB, Printed Circuit Board}, part of the RiNgDove EDA +suite.") + (license license:gpl2+))) + (define-public sigrok-cli (package (name "sigrok-cli") @@ -967,7 +2229,7 @@ them usable as simple logic analyzer and/or oscilloscope hardware.") (define-public symbiyosys (package (name "symbiyosys") - (version "0.55") + (version "0.58") (source (origin (method git-fetch) @@ -976,7 +2238,7 @@ them usable as simple logic analyzer and/or oscilloscope hardware.") (commit (string-append "v" version)))) (file-name (git-file-name name version)) (sha256 - (base32 "1nxaijz7afpa1y8i4pbpadgv7kpz8rk02j42kxjpv117lxd3g9za")))) + (base32 "0fja71y1wkqdwc3cwwk9ifaf33hhnxr8khlj9fhadbcc66rg1s56")))) (build-system gnu-build-system) (arguments (list @@ -1027,22 +2289,57 @@ them usable as simple logic analyzer and/or oscilloscope hardware.") verification flows.") (license license:isc))) +(define-public systemc + (package + (name "systemc") + (version "3.0.1") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/accellera-official/systemc") + (commit version))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1c8brlv3702p2ivifai9929bg20y30jb301ap0gdmz305q8mcb33")))) + (native-inputs (list perl)) + (build-system cmake-build-system) + (arguments + (list + #:modules '((guix build cmake-build-system) + ((guix build gnu-build-system) #:prefix gnu:) + (guix build utils)) + #:phases + #~(modify-phases %standard-phases + (replace 'check (assoc-ref gnu:%standard-phases 'check))))) + (home-page "https://systemc.org/") + (synopsis "Library for event-driven simulation") + (description + "SystemC is a C++ library for modeling concurrent systems, and the +reference implementation of IEEE 1666-2011. It provides a notion of timing as +well as an event-driven simulations environment. Due to its concurrent and +sequential nature, SystemC allows the description and integration of complex +hardware and software components. To some extent, SystemC can be seen as +a Hardware Description Language. However, unlike VHDL or Verilog, SystemC +provides sophisticated mechanisms that offer high abstraction levels on +components interfaces. This, in turn, facilitates the integration of systems +using different abstraction levels.") + ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf + (license license:asl2.0))) + (define-public uhdm (package (name "uhdm") - (version "1.84") + (version "1.86") (source (origin (method git-fetch) (uri (git-reference (url "https://github.com/chipsalliance/UHDM/") - (commit (string-append "v" version)) - ;; avoid submodules, and use guix packages capnproto and - ;; googletest instead - (recursive? #f))) + (commit (string-append "v" version)))) (file-name (git-file-name name version)) (sha256 - (base32 "06i06wfyymhvmpnw79lgb84l9w9cyydvnr7n3bgmgf8a77jbxk2y")))) + (base32 "0nsy385frxz5v7i757h1x59xkl21asz3h2fk1nyvx37z8cj0kd3z")))) (build-system gnu-build-system) (arguments (list @@ -1053,12 +2350,15 @@ verification flows.") #:test-target "test" #:make-flags #~(list - "ADDITIONAL_CMAKE_OPTIONS=-DUHDM_USE_HOST_CAPNP=On -DUHDM_USE_HOST_GTEST=On" - (string-append "PREFIX=" - #$output)))) - (native-inputs (list cmake-minimal googletest pkg-config python-wrapper - swig)) - (inputs (list capnproto openssl python-orderedmultidict zlib)) + (string-append + "ADDITIONAL_CMAKE_OPTIONS=-DUHDM_USE_HOST_CAPNP=On" + ;; " -DUHDM_WITH_PYTHON=On" ;FIXME + " -DUHDM_USE_HOST_GTEST=On") + (string-append "PREFIX=" #$output)))) + (native-inputs + (list cmake-minimal googletest pkg-config python-wrapper swig)) + (inputs + (list capnproto openssl python-orderedmultidict zlib)) (home-page "https://github.com/chipsalliance/UHDM/") (synopsis "Universal Hardware Data Model") (description @@ -1066,6 +2366,65 @@ verification flows.") VPI Interface, Elaborator, Serialization, Visitor and Listener.") (license license:asl2.0))) +(define-public verilator + (package + (name "verilator") + (version "5.040") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/verilator/verilator/") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 + (base32 "0xw2w7fikli3jffwd819rx8bwbh3zsymhrn3zbq34glklff07rsb")))) + (native-inputs + (list autoconf + automake + bison + cmake-minimal + flex + gdb/pinned + gettext-minimal + help2man + python-distro + python-minimal + which)) + (inputs + (list perl python systemc)) + (build-system gnu-build-system) + (arguments + (list + #:phases + #~(modify-phases %standard-phases + (replace 'bootstrap + (lambda _ (invoke "autoconf"))) + (add-after 'unpack 'adjust-source + (lambda _ + (substitute* "bin/verilator" + (("/bin/echo") "echo")))) + (add-before 'check 'set-SYSTEMC_ROOT + (lambda _ + (setenv "SYSTEMC_ROOT" #$(this-package-input systemc)))) + (add-before 'check 'disable-gdb-safe-path + (lambda _ + (setenv "HOME" (getcwd)) + (mkdir-p (string-append (getcwd) "/.config/gdb")) + (with-output-to-file + (string-append (getcwd) "/.config/gdb/gdbinit") + (lambda () + (display "set auto-load safe-path /")))))) + #:test-target "test")) + (home-page "https://www.veripool.org/verilator/") + (synopsis "Verilog/SystemVerilog simulator") + (description + "Verilator transforms the specified Verilog or SystemVerilog code by +reading it, performing lint checks, and optionally inserting assertion checks +and coverage-analysis points. It outputs single- or multi-threaded +@file{.cpp} and @file{.h} files.") + (license license:lgpl3))) + (define-public xoscope (package (name "xoscope") @@ -1088,3 +2447,123 @@ from ALSA, ESD, and COMEDI sources. This package currently does not include support for ESD sources.") (home-page "https://xoscope.sourceforge.net/") (license license:gpl2+))) + +(define-public yosys + (package + (name "yosys") + (version "0.58") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/YosysHQ/yosys") + (commit (string-append "v" version)))) + (sha256 + (base32 "13095d587dvnj6n1fhw5whda7qhafmmng0qz6qa52cdxriz63kka")) + (file-name (git-file-name name version)))) + (build-system gnu-build-system) + (arguments + (list + #:test-target "test" + #:make-flags + #~(list (string-append "CC=" + #$(cc-for-target)) + (string-append "CXX=" + #$(cxx-for-target)) + (string-append "PREFIX=" + #$output)) + #:phases + #~(modify-phases %standard-phases + (add-before 'configure 'fix-paths + (lambda* (#:key inputs #:allow-other-keys) + (substitute* "backends/smt2/smtio.py" + (("\\['z3") + (string-append "['" + (search-input-file inputs "bin/z3")))) + (substitute* "kernel/fstdata.cc" + (("vcd2fst") + (search-input-file inputs "bin/vcd2fst"))) + (substitute* "kernel/driver.cc" + (("^#include \"libs/cxxopts/include/cxxopts.hpp\"") + "#include <cxxopts.hpp>")) + (substitute* '("passes/cmds/show.cc" "passes/cmds/viz.cc") + (("exec xdot") + (string-append "exec " + (search-input-file inputs "bin/xdot"))) + (("dot -") + (string-append (search-input-file inputs "bin/dot") " -")) + (("fuser") + (search-input-file inputs "bin/fuser"))))) + (replace 'configure + (lambda* (#:key make-flags #:allow-other-keys) + (apply invoke "make" "config-gcc" make-flags))) + (add-after 'configure 'use-external-abc + (lambda* (#:key inputs #:allow-other-keys) + (substitute* '("Makefile") + (("ABCEXTERNAL \\?=") + (string-append "ABCEXTERNAL = " + (search-input-file inputs "/bin/abc")))))) + (add-after 'install 'add-symbolic-link + (lambda* (#:key inputs #:allow-other-keys) + ;; Previously this package provided a copy of the "abc" + ;; executable in its output, named "yosys-abc". Create a + ;; symbolic link so any external uses of that name continue to + ;; work. + (symlink (search-input-file inputs "/bin/abc") + (string-append #$output "/bin/yosys-abc")))) + (add-after 'install 'keep-pmgen-py + (lambda* (#:key inputs #:allow-other-keys) + ;; pmgen.py is required by some yosys plugins. + (install-file (search-input-file inputs + "/passes/pmgen/pmgen.py") + (string-append #$output "/bin")))) + (add-after 'install 'wrap + (lambda* (#:key inputs #:allow-other-keys) + (wrap-program (string-append #$output "/bin/yosys-witness") + `("GUIX_PYTHONPATH" ":" prefix + (,(getenv "GUIX_PYTHONPATH"))))))))) + (native-inputs (list bison + cxxopts ;header-only library + flex + gawk ;for the tests and "make" progress pretty-printing + iverilog ;for the tests + pkg-config + python + tcl)) ;tclsh for the tests + (inputs (list abc-yosyshq + bash-minimal + graphviz + gtkwave + libffi + psmisc + python + python-click + readline + tcl + xdot + z3 + zlib)) + (home-page "https://yosyshq.net/yosys/") + (synopsis "FPGA Verilog RTL synthesizer") + (description "Yosys synthesizes Verilog-2005.") + (license license:isc))) + +(define-public yosys-clang + (package + (inherit yosys) + (name "yosys-clang") + (arguments + (substitute-keyword-arguments (package-arguments yosys) + ((#:make-flags _ #f) + #~(list "CC=clang" + "CXX=clang++" + (string-append "PREFIX=" #$output))) + ((#:phases phases) + #~(modify-phases #$phases + (replace 'configure + (lambda* (#:key make-flags #:allow-other-keys) + (apply invoke "make" "config-clang" make-flags))))))) + (inputs + (modify-inputs (package-inputs yosys) + (append clang))) + (synopsis "FPGA Verilog RTL synthesizer (Clang variant)"))) |