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-rw-r--r--gnu/packages/fpga.scm8
1 files changed, 4 insertions, 4 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index e12bd6dce4..377aeeb251 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -147,15 +147,15 @@ formal verification. This is the Yosyshq fork of ABC.")
(define-public apycula
(package
(name "apycula")
- (version "0.22")
+ (version "0.23")
;; The pypi tar.gz file includes the necessary .pickle files, not available
;; in the home-page repository.
(source
(origin
(method url-fetch)
- (uri (pypi-uri "Apycula" version))
+ (uri (pypi-uri "apycula" version))
(sha256
- (base32 "15xwmi6z2p7jz17l5bqs511yh8jis1dacqc8fypx49jysl7h0apd"))))
+ (base32 "1kk9hi8zhdp1am5vj716lwlmrs31lxrwhdbbc4qsad470dcjqs57"))))
(build-system pyproject-build-system)
(arguments (list #:tests? #f)) ;requires Gowin EDA tools
(inputs (list python-crc))
@@ -854,7 +854,7 @@ and coverage-analysis points. It outputs single- or multi-threaded
(synopsis "Generic pipelined FFT core generator")
(description "fftgen produces @acronym{FFT, fast-Fourier transforms}
hardware designs in Verilog.")
- (home-page "https://zipcpu.com/")
+ (home-page "https://github.com/ZipCPU/zipcpu/")
(license license:lgpl3+))))
(define-public openfpgaloader