diff options
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 112 |
1 files changed, 58 insertions, 54 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index ff3bbe52f0..4cf534e815 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -147,15 +147,15 @@ formal verification. This is the Yosyshq fork of ABC.") (define-public apycula (package (name "apycula") - (version "0.22") + (version "0.23") ;; The pypi tar.gz file includes the necessary .pickle files, not available ;; in the home-page repository. (source (origin (method url-fetch) - (uri (pypi-uri "Apycula" version)) + (uri (pypi-uri "apycula" version)) (sha256 - (base32 "15xwmi6z2p7jz17l5bqs511yh8jis1dacqc8fypx49jysl7h0apd")))) + (base32 "1kk9hi8zhdp1am5vj716lwlmrs31lxrwhdbbc4qsad470dcjqs57")))) (build-system pyproject-build-system) (arguments (list #:tests? #f)) ;requires Gowin EDA tools (inputs (list python-crc)) @@ -571,8 +571,8 @@ Simulator Trace} files.") ;; XXX: The latest version tag (0.9.2) was placed in 2019, there are latest ;; changes supporting Python 3.11 on master branch, see ;; <https://github.com/m-labs/migen/issues/259>. - (let ((commit "2828df54594673653a641ab551caf6c6b1bfeee5") - (revision "0")) + (let ((commit "6e3a9e150fb006dabc4b55043d3af18dbfecd7e8") + (revision "1")) (package (name "python-migen") (version (git-version "0.9.2" revision commit)) @@ -585,12 +585,11 @@ Simulator Trace} files.") (commit commit))) (file-name (git-file-name name version)) (sha256 - (base32 "0my2jwrb64n39dfcipiw9s2cbg1r4s6zh4ybf4dwid9hk86fi6hs")))) + (base32 "1hibhjnj5b3ka5y4nnqx9zp5w730gfqfa3r5injpa14i4cz6bj1n")))) (build-system pyproject-build-system) (native-inputs (list python-pytest - python-setuptools - python-wheel)) + python-setuptools-next)) (propagated-inputs (list python-colorama)) (home-page "https://m-labs.hk/gateware/migen/") @@ -795,61 +794,66 @@ using different abstraction levels.") (list perl python systemc)) (build-system gnu-build-system) (arguments - '(#:phases - (modify-phases %standard-phases - (replace 'bootstrap - (lambda _ (invoke "autoconf"))) - (add-after 'unpack 'adjust-source - (lambda _ - (substitute* "bin/verilator" - (("/bin/echo") "echo")))) - (add-before 'check 'disable-gdb-safe-path - (lambda _ - (setenv "HOME" (getcwd)) - (mkdir-p (string-append (getcwd) "/.config/gdb")) - (with-output-to-file (string-append (getcwd) "/.config/gdb/gdbinit") - (lambda () - (display "set auto-load safe-path /")))))) - #:test-target "test")) + (list + #:phases + #~(modify-phases %standard-phases + (replace 'bootstrap + (lambda _ (invoke "autoconf"))) + (add-after 'unpack 'adjust-source + (lambda _ + (substitute* "bin/verilator" + (("/bin/echo") "echo")))) + (add-before 'check 'disable-gdb-safe-path + (lambda _ + (setenv "HOME" (getcwd)) + (mkdir-p (string-append (getcwd) "/.config/gdb")) + (with-output-to-file + (string-append (getcwd) "/.config/gdb/gdbinit") + (lambda () + (display "set auto-load safe-path /")))))) + #:test-target "test")) (home-page "https://www.veripool.org/verilator/") (synopsis "Verilog/SystemVerilog simulator") (description - "Verilator transforms the specified Verilog or SystemVerilog code by reading it, -performing lint checks, and optionally inserting assertion checks and -coverage-analysis points. It outputs single- or multi-threaded @file{.cpp} -and @file{.h} files.") + "Verilator transforms the specified Verilog or SystemVerilog code by +reading it, performing lint checks, and optionally inserting assertion checks +and coverage-analysis points. It outputs single- or multi-threaded +@file{.cpp} and @file{.h} files.") (license license:lgpl3))) (define-public fftgen - (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08") ;no releases - (revision "0")) + (let ((commit "3378b77d83a98b06184656a5cb9b54e50dfe4485") ;no releases + (revision "1")) (package (name "fftgen") (version (git-version "0" revision commit)) - (source (origin - (method git-fetch) - (uri (git-reference - (url "https://github.com/ZipCPU/dblclockfft") - (commit commit))) - (file-name (git-file-name name version)) - (sha256 - (base32 - "0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd")))) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/ZipCPU/dblclockfft") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1rvln871wjkbbqnv88jnx328xlhn5sgbr8fglk3ajnd9rwgiq3jg")))) (build-system gnu-build-system) (arguments - `(#:tests? #f ;no tests - #:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2 - #:phases (modify-phases %standard-phases - (delete 'configure) - (replace 'install - (lambda* (#:key outputs #:allow-other-keys) - (let ((bin (string-append (assoc-ref outputs "out") - "/bin"))) - (install-file "sw/fftgen" bin))))))) + (list + #:test-target "bench-test" + #:make-flags #~(list "CFLAGS=-g -O2") ;default flags lack -O2 + #:phases + #~(modify-phases %standard-phases + (delete 'configure) + (replace 'install + (lambda _ + (install-file "sw/fftgen" + (string-append #$output "/bin"))))))) + (native-inputs (list bc fftw python-minimal verilator which)) (synopsis "Generic pipelined FFT core generator") (description "fftgen produces @acronym{FFT, fast-Fourier transforms} hardware designs in Verilog.") - (home-page "https://zipcpu.com/") + (home-page "https://github.com/ZipCPU/zipcpu/") (license license:lgpl3+)))) (define-public openfpgaloader @@ -899,8 +903,8 @@ to @samp{info \"(guix) Base Services\"} for examples.") (license license:asl2.0))) (define-public python-hdlmake - (let ((commit "48260fb0d7ace3ff2ee124121a5780a226513077") - (revision "2")) + (let ((commit "c56cb8efa2000d06cec698f0149bc4ca4ef4e5bc") + (revision "3")) (package (name "python-hdlmake") (version (git-version "3.3" revision commit)) @@ -912,16 +916,16 @@ to @samp{info \"(guix) Base Services\"} for examples.") (commit commit))) (file-name (git-file-name name version)) (sha256 - (base32 "1s36gc5g3v20x2v26d45hfw2x9r7k54lj7sggz94qi7ydbi1ng41")))) + (base32 "1w4b0g015rzfypr8sjyr8xqij6s2p5qxhxraswrhjvg1w86b6s36")))) (build-system pyproject-build-system) (arguments (list #:phases #~(modify-phases %standard-phases (add-before 'check 'chdir (lambda _ (chdir "testsuite")))) #:test-flags #~(list "test_all.py"))) - (native-inputs (list python-pytest python-setuptools python-wheel)) + (native-inputs (list python-pytest python-setuptools-next)) (propagated-inputs (list python-networkx python-six)) - (home-page "https://gitlab.com/ohwr/project/hdl-make/") + (home-page "https://ohwr.gitlab.io/project/hdl-make/") (synopsis "Generate multi-purpose makefiles for HDL projects") (description "Hdlmake helps manage and share @acronym{HDL, hardware description |